1. Field of the Invention
The present invention relates to integrable semiconductor circuits for use as a frequency divider or a binary counter.
2. Description of the Prior Art
A frequency divider (or asynchronous pulse counters) are described in "Philips techn. Rdsch.", 38, No. 2, 1979 at pages 47-62 which are constructed utilizing bistable circuits (flip-flop elements or cells) functioning according to the master-slave principle. Such conventional circuits utilize transistors of the same type connected to load resistors to form a network. A signal sequence consisting of a series of identical pulses to be processed is supplied to the inputs of an input stage which is formed by a differential amplifier. The differential amplifier consists of two transistors having respective current input electrodes which are connected to each other and to a grounded terminal through a constant current source. The current output electrodes of the transistors comprising the differential amplifier are connected to a supply voltage terminal through the aforementioned network. The network forms a bistable circuit in combination with the input circuit, this bistable circuit functioning according to the master-slave principle and having two outputs at which output pulses are tapped.
Known circuits of the type described above are generally manufactured using bipolar transistors, particularly of the NPN type. It is also possible, however, to construct such circuits using field effect transistors, particularly self-inhibiting metal-oxide-semiconductor field effect transistors. As used herein, the term "current input electrode" when used in connection with bipolar transistors means the emitter terminal, the term "current output electrode" means the collector terminal, and the term "control electrode" means the base terminal. For field effect transistors, the term "current input electrode" means the source terminal, the term "current output electrode" means the drain terminal, and the term "control electrode" means the gate terminal.
Conventional frequency divider circuits (or digital counter circuits) of the type described above including a plurality of divider or counter stages exhibit a dynamic behavior which places different demands upon the different stages. Whereas the first stage must process the input frequency, that is, the highest frequency, the second stage receives only half of that frequency, and in general the p.sup.th stage generally only receives 1/(2.sup.p-1) of the input frequency.
It has been generally recognized that the occurrence of increasingly reduced dynamic demands along the chain of divider or counter stages permits staggering the current division to the individual stages in order to reduce the overall power dissipation of the flip-flop chain forming the divider or counter circuit. For example, the current supplied to each individual stage in the chain may be one-half of the current supplied to the immediately preceding stage in order to meet a desired power dissipation/transit time product which is fixed by the particular technology which is utilized to manufacture the circuit.